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    Introduction to analog circuits

    2.44
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    Diode and its equation

    6.38
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    Diode parameters

    3.32
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    Diode clipper circuits - A

    11.55
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    Diode clipper circuits - B

    7.45
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    Biased clipper

    9.09
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    Clipper using zener diode

    13.42
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    Introduction to Number System

    10.55
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    Number System Conversion

    24.04
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    Numericals Based on Number System-Part 1

    21.36
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    Numericals Based on Number System-Part 2

    18.14
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    Complement Number Representation

    19.31
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    Clamper using diode

    22.16
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    Voltage doubler /tripler/quadrupler

    10.57
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    Rectifier Using Diode

    12.4
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    Signed Number Representation for Binary

    32
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    Important Properties of 1's and 2's Complement Numbers

    17.43
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    Concept of Overflow and Sign Extension

    18.52
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    Subtraction Using R's and (R-1)'s Complement Method

    34.04
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    DC load line of Diode

    7.55
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    Diode Numerical Session 1

    13.39
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    Diode Numerical Session 2

    8.41
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    Diode Numerical Session 3

    12.15
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    Diode Numerical Session 4

    9.36
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    Diode Numerical Session 5

    8.11
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    Binary Codes

    30.06
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    Generation of Gray Code

    14.41
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    Conversion of Binary to Gray and Gray to Binary Codes

    12.57
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    Gate Numerical on Number System Part 1

    28
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    Gate Numerical on Number System Part 2

    25.07
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    BJT Introduction

    9.04
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    BJT CE Configuration

    11.03
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    BJT BJT Q Point & stability

    13.51
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    BJT Biasing circuits

    15.01
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    Boolean Laws

    25.16
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    Concept of Minterms and Maxterm

    22.32
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    Problems Based on Minterms and Maxterms

    32.37
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    Complementing the Function

    11.25
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    BJT Small Signal models

    16.38
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    BJT Small Signal AC analysis

    13.05
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    BJT Frequency response

    24.01
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    Introduction to K-Map

    15.49
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    Grouping Techniques in K-Map

    31.56
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    Numerical Based on Boolean Algebra

    28.24
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    BJT As a switch & CB/CC amplifier

    10.36
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    BJT Numerical Session 1

    16.11
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    BJT Numerical Session 2

    11
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    BJT Numerical Session 3

    11.13
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    BJT Numerical Session 4

    8.35
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    BJT Numerical Session 5

    9.56
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    Basic Logic Gates

    6.26
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    Universal Logic Gates

    16.25
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    Numericals Based on Universal Logic Gates

    22.3
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    Ex-OR Gate

    13.37
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    Important Properties of Ex-OR Gate

    20.02
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    Gate Numericals on Logic Gates

    36.04
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    Introduction to Timer IC 555

    10.54
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    555 MMV

    11.01
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    555 AMV

    10.35
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    Introduction to Combinational Logic Circuit

    11.24
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    Half Adder

    7.14
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    Half Subtractor

    7.17
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    Full Adder

    12.23
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    Implementing Full Adder with Half Adder

    10.46
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    Concept of Comparator

    20.47
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    4-Bit Parallel/ Ripple Adder

    15.55
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    4-Bit Serial Adder

    18.46
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    MOSFET Basics

    12.1
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    MOSFET Biasing

    9.3
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    MOSFET AC model & amplifier

    10.51
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    As square wave generator

    4.33
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    Timer-555 : Numerical Session 1

    7.07
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    Timer -555 : Numerical Session 2

    6.28
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    4-Bit Adder/ Subtractor

    11.03
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    Encoder

    8.11
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    Decoder

    11.36
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    Full Adder Using 3:8 Decoder

    14.56
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    Decoder Expansion

    17.34
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    Concept of Demultiplexer

    7.37
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    Decoder Using Demultiplexer

    6.35
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    Concept of Multiplexer

    8.47
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    Multiplexer Expansion

    14.4
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    CMOS using MOSFET

    9.44
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    MOSFET Frequency response

    7.49
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    MOSFET Numerical Session 1

    10.05
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    MOSFET Numerical Session 2

    7.5
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    MOSFET Numerical Session 3

    10
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    MOSFET Numerical Session 4

    8.26
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    MOSFET Numerical Session 5

    4.21
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    Implementing 2:1 Mux Using 4:1 Mux

    8.4
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    2:1 Multiplexer as Universal Logic Circuit

    16.03
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    4:1 Multiplexer as Universal Logic Gate

    5.52
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    Gate Problems on Mux, Decoder and Decoder

    29.13
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    Introduction to Sequential Logic Circuit

    14.44
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    NOR Latch

    14.54
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    NAND Latch

    10.32
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    Introduction

    14.57
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    Comparison and Analysis of Negative Feedback Amplifier

    16.44
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    Negative feedback Numerical Session 1

    7.06
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    Problem with RS Latch

    17.43
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    Delay Latch/Flip Flop

    4.49
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    JK Latch and T- Latch

    7.48
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    Excitation Table for all Latches/Flip Flops

    19.52
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    Latch/Flip Flop Conversion Concept

    23.22
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    SR Latch to JK Latch Conversion

    18.09
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    DA using BJT

    14.37
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    DA Gain Equation

    8.47
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    Negative feedback Numerical Session 2

    8.16
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    Negative feedback Numerical Session 3

    8.28
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    Negative feedback Numerical Session 4

    6
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    D Latch to JK Latch Conversion

    8.58
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    D Latch to T Latch Conversion

    6.46
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    Concept of Triggering

    14.17
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    Difference between Latch and Flipflop

    10.59
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    Behaviour of Flip Flop in Toggle Mode

    13.19
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    Race Around Condition in JK Latch

    14.44
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    Master-Slave JK Flip Flop

    9.03
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    Introduction to Shift Register

    9.17
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    CCS and CM

    11.36
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    DA Using MOSFET and CCS & CM

    8.59
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    DA Numerical Session 1

    13.37
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    DA Numerical Session 2

    7.34
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    DA Numerical Session 3

    4.53
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    Classification of Shift Register

    28.48
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    Ring Counter

    17.46
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    Twisted Ring Counter

    14.12
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    Introduction to Asynchronous Counter

    10.03
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    Asynchronous Up Counter

    15.14
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    Asynchronous Down Counter

    19.45
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    Introduction and Two Stage Analysis

    25.48
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    Cascode Amplifier and Darlington Amplifier

    15.25
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    Asynchronous Up/Down Counter

    14.1
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    Introduction To Asynchronous MOD Counter

    17.3
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    Designing Asynchronous MOD 10 Counter

    11.53
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    Introduction to Synchronous Counter

    11.55
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    Designing Synchronous Counter_ Part 1

    12.59
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    Designing Synchronous Counter_ Part 2

    15.03
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    Finite State Machine

    10.45
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    Three stage amplifier

    5.24
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    Multistage Amplifier Numerical Session 1

    15.54
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    Multistage Amplifier Numerical Session 2

    8.28
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    Multistage Amplifier Numerical Session 3

    12.18
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    Multistage Amplifier Numerical Session 4

    8.43
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    Non Overlapping Sequence Detector

    16.52
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    Overlapping Sequence Detector

    28.48
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    Gate Numericals Based on Sequential Logic Circuit

    33.18
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    Gate Numericals on FSM

    22.36
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    OP-AMP Introduction

    17.14
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    OP-AMP as aquare wave generator

    9.12
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    OP-AMP First order active filters

    15.43
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    Introduction to ADC and DAC

    10.4
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    Concept of Specifications of DAC

    16.53
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    Binary weighted Resistor type DAC

    18.53
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    R-2R Ladder type DAC

    7.43
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    Numerical on DAC

    14
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    Counter Type ADC

    23.27
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    Successive Approximation Register type DAC

    20.18
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    Flash Type ADC

    28.52
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    Op-Amp Second Order Active Filters and Instrumentation Amplifier

    13.01
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    Op-Amp Oscillator and Triangular Wave Generator

    14.57
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    Op-Amp Log Circuits and Precision Rectifier

    16.14
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    Introduction Registered Organisation Memory Basics

    24.51
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    Introduction to Register Set

    17.34
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    Single Accumulator Organization : Size 1

    18.39
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    Single Accumulator Organization : Purpose 2

    26.5
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    Single Accumulator Organization : Connections 3

    21.41
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    OP-AMP SCHMITT Trigger circuits

    9.42
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    OP-AMP As comparator

    4.45
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    OPAMP and Application Numerical Session 1

    7.32
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    OPAMP and Application Numerical Session 2

    10.23
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    OPAMP and Application Numerical Session 3

    10.03
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    General Register Organization 1

    17.34
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    General Register Organization 2

    14.23
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    General Register Organization 3

    8.11
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    Flag Register

    23.16
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    Stack Organization 1

    29.07
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    Stack Organization 2

    9.35
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    Numerical session 1

    8.25
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    Numerical session 2

    8.01
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    Numerical session 3

    9.29
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    Numerical session 4

    8.37
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    OPAMP and Application Numerical Session 4

    7.17
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    OPAMP and Application Numerical Session 5

    11.25
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    Instruction Cycle 1

    11.52
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    Instruction Cycle 2

    15.14
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    Instruction Cycle 3

    12.01
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    Instruction Formats : Number of Operands 1

    16.2
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    Instruction Formats : Number of Operands 2

    15.41
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    Instruction Formats : Number of Operands 3

    14.53
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    Instruction Formats : Location of the Operand 1

    10.29
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    Instruction Formats : Location of the Operand 2

    17.59
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    Definition and Parameters

    10.04
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    Zener Voltage regulator

    11.14
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    Voltage regulator Numerical Session 1

    11.23
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    Voltage regulator Numerical Session 2

    7.59
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    Instruction Formats : Location of the Operand 3

    16.54
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    Instruction Formats : Location of the Operand 4

    16.5
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    Instruction Formats : Sub Routine Call and Return

    22.31
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    Instruction Formats : Register Reference Instructions

    23.25
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    Instruction Formats : I O Reference Instructions

    11.28
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    Voltage regulator Numerical Session 3

    7.47
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    Voltage regulator Numerical Session 4

    6.57
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    Voltage regulator Numerical Session 5

    10.17
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    Types of Instructions1

    18.57
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    Types of Instructions2

    14.59
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    Types of Instructions 3

    13.2
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    Addressing Modes 1

    16.18
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    Addressing Modes 2

    15.49
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    Addressing Modes 3

    17.53
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    Introduction

    10.23
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    Class A power amplifier

    12.53
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    Class B power amplifier

    12.13
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    Class AB power amplifier

    6.35
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    Class C PA and Heat Sink

    9.25
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    Comparison

    5.17
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    Power amplifier Numerical Session 1

    7.41
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    Power amplifier Numerical Session 2

    6.55
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    Power amplifier Numerical Session 3

    5.07
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    Control Unit 1

    12
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    Control Unit 2

    17.22
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    Control Unit 3

    22.29
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    ALU Design 1

    16.47
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    ALU Design 2

    15.08
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    ALU Design 3

    28.02
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    Model Gate Question On Instruction size

    15.46
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    GATE Question 1

    5.41
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    GATE Question 2

    6.43
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    GATE Question 3

    5.02
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    GATE Question 4

    4.1
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    GATE Question 5

    7.41
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    GATE Question 6

    8.1
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    GATE Question 7

    20.15
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    GATE Question 8

    14.13
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    GATE Question 9

    11.13
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    GATE Question 10

    5.12
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    GATE Question 11

    12.13
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    GATE Question 12

    4.38
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    GATE Question 13

    9.55
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    GATE Question 14

    3.23
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    GATE Question 15

    5.08
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    GATE Question 16

    10.57
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    GATE Question 17

    10.05
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    GATE Question 18

    9.1
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    GATE Question 19

    11.34
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    GATE Question 20

    13.58
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    Introduction to Pipeling: Throughput

    8.48
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    Introduction to Pipeling: Parallel Processing

    11.55
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    Data Pipeline 1

    10.04
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    Data Pipeline 2

    18.26
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    Speed Up

    23.01
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    Speed Up Example

    6.02
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    Instruction Pipeline 1

    13.14
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    Instruction Pipeline 2

    11.25
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    Hazards in Pipeline 1

    8.29
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    Hazards in Pipeline 2

    9.4
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    Hazards in Pipeline 3

    8.5
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    Handling Hazards 1

    6.16
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    Handling Hazards 2

    14.46
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    Handling Hazards 3

    6.15
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    Handling Hazards 4

    18.17
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    Important Formulae

    12.43
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    Example 1

    6.13
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    Pipelining Gate Question 1

    8.51
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    Pipelining Gate Question 2

    3.43
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    Pipelining Gate Question 3

    22.3
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    Pipelining Gate Question 4

    19.13
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    Pipelining Gate Question 5

    3.41
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    Pipelining Gate Question 6

    4.38
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    Pipelining Gate Question 7

    6.41
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    Pipelining Gate Question 8

    8.02
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    Pipelining Gate Question 9

    13.5
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    Pipelining Gate Question 10

    5.04
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    Pipelining Gate Question 11

    6.29
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    Pipelining Gate Question 12

    6.52
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    Pipelining Gate Question 13

    4.29
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    Pipelining Gate Question 14

    9.05
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    Pipelining Gate Question 15

    5.03
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    Pipelining Gate Question 16

    9.28
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    Types of Elements

    13.57
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    Energy Sources

    12.03
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    Problem based on Energy Sources

    8.18
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    Kirchoff's Law

    18.32
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    Introduction to Control System

    37.26
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    Need of Laplace Transform in Control System

    31.05
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    Problems on Laplace Transform

    11.14
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    Transfer Function - Part 1

    28.26
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    Energy and Power for R, L and C

    9.18
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    Problems based on Energy and Power

    36.42
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    Equivalent Circuits

    26.04
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    Problems based on Equivalent Cicuits Part 1

    22.02
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    Problems based on Equivalent Cicuits Part 2

    24.34
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    Transfer Function - Part 2

    41.12
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    Problems based on Transfer Function

    37.05
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    Initial Value & Final Value Theorem

    43.48
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    Solving DC Circuits using KVL/KCL_ Part1

    9.26
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    Solving DC Circuits using KVL/KCL_ Part2

    23.01
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    Solving DC Circuits using KVL/KCL_ Part3

    26.22
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    Solving DC Circuits using KVL/KCL_ Part4

    20.03
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    Block Diagram Reduction

    45.52
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    Problem based on Block Diagram Reduction - Part 1

    14.51
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    Problem based on Block Diagram Reduction - Part 2

    19.59
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    Introduction to Signal Flow Graph

    24.5
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    Problem based on Signal Flow Graph - Part 1

    24.43
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    Problem based on Signal Flow Graph - Part 2

    16.44
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    Problem based on Signal Flow Graph - Part 3

    30.05
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    Introduction to Thevenin's and Norton's Theorem

    17.43
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    Problems on TEC and NEC- Part 1

    21.15
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    Problems on TEC and NEC- Part 2

    24.19
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    GATE problem based on Block diagram and SFG

    23.03
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    Introduction to Time Domain Analysis

    29.26
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    Standard 1st Order System Analysis

    23.43
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    Introduction to Superposition Theorem

    11.42
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    Introduction to Maximum Power Transfer Theorem

    40.58
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    Standard 2nd Order System Analysis - Part 1

    54.23
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    Standard 2nd Order System Analysis - Part 2

    48.06
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    Problems on M.P.T. - Part 1

    16.32
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    Introduction to Two Port Network_ Part 1

    23.16
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    Equivalent Circuits in Two Port Network

    21.33
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    Standard 2nd Order System Analysis - Part 3

    25.11
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    Time Domain Specifications

    21.02
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    Location of Poles and Time Domain Specifications

    15.53
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    Problems on 1st Order and 2nd Order Systems

    43.46
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    Interconnection of Two Port Networks

    18.48
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    Symmetricity and Reciprocity in Two Port Network

    34
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    Introduction to Steady State Error

    7.53
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    Static Error Analysis - Part 1

    27.25
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    Static Error Analysis - Part 2

    49.52
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    Standard Two Port Networks and Parameters

    20.57
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    Numericals on Two Port Network _ Part 1

    28.43
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    Numericals on Two Port Network _ Part 2

    20.35
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    Numericals on Two Port Network _ Part 3

    30.24
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    Dynamic Error analysis

    26.58
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    Problems on Error Analysis

    47
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    Introduction to Transient Analysis

    22.46
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    Behaviour of R, L and C for t>0

    11.15
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    Numericals on Tansients_Part 1

    15.25
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    Concept of Stability

    8.1
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    Routh Hurwitz's Criterion Part_1

    11
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    Routh Hurwitz's Criterion Part_2

    50.21
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    Routh Hurwitz's Criterion Part_3

    23.35
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    Numericals on Tansients_Part 2

    51.42
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    Routh Hurwitz's Criterion Part_4

    16.28
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    Introduction to Root Locus

    23.12
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    Root Locus_Part 1

    47.33
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    Root Locus_Part 2

    25.26
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    Numericals on Tansients_Part 3

    28.28
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    Numericals on Tansients_Part 4

    35.43
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    Root Locus_Part 3

    38.57
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    Problems on Routh Hurwitz's Criterion

    25.21
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    Problems on Root Locus

    20.47
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    Introduction to Laplace Transformation

    12.05
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    Application of Laplace Transform in Electrical Circuits

    13.3
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    Numericals on Laplace Transformation _ Part 1

    18.09
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    Numericals on Laplace Transformation _ Part 2

    25.58
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    Introduction to Frequency Domain Analysis

    24.06
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    FDA for 2nd order system

    41.57
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    Polar Plot - Part 1

    24.31
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    Polar Plot - Part 2

    57.56
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    A.C. Fundamentals

    8.4
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    Concept of Average and RMS values

    17.26
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    Numericals on Average and RMS values

    25.27
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    Polar Plot - Part 3

    38.06
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    Polar Plot - Part 4

    48.48
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    Polar Plot - Part 5

    57.31
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    Vector Representation

    15.57
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    Behaviour of R, L and C in A.C. Circuits

    22.11
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    RL Series Circuit

    10.59
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    RC series Circuit

    12.45
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    Stability in Frequency Domain

    9.42
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    Nyquist Plot - Part 1

    41.13
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    Nyquist Plot - Part 2

    16.37
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    Nyquist Stability Criteria

    28.36
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    RLC Series Circuit

    9.49
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    Classification of Power

    14.06
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    Numericals on Fundamentals of A.C. Circuits _ Part 1

    24.35
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    Numericals on Fundamentals of A.C. Circuits _ Part 2

    19.02
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    Examples on Nyquist Stability Criteria

    42.17
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    Numericals on Nyquist Stability Criteria

    31.32
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    Relative Stability in Frequency Domain

    40.22
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    Numericals on Fundamentals of A.C. Circuit - Part 3

    19.29
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    Numericals on Fundamentals of A.C. Circuit - Part 4

    14.52
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    Numericals on Fundamentals of A.C. Circuit - Part 5

    16.56
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    Introduction to Bode Plot

    37.2
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    How to Draw Bode Plot

    56.19
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    Numericals on Bode plot

    12.26
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    Relative Stability using Bode Plot

    11.5
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    Numericals on Fundamentals of A.C. Circuit - Part 6

    20.14
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    Series Resonance in A.C. Circuits

    24.06
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    Parallel RL Circuit

    9.44
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    Introduction to Controllers and Compensators

    12.08
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    Compensators

    49.06
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    Controllers

    21.4
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    Numericals on Controllers and Compensators

    10.5
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    Parallel RC Circuit

    8.01
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    Parallel RLC Circuit

    7.06
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    Parallel Resonance in A.C. Circuits_ Part 1

    24.15
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    Parallel Resonance in A.C. Circuits_ Part 2

    12.38
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    Introduction to State Space Analysis

    69.29
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    State Space Analysis in electrical circuits

    27.02
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    Concept of Q-Factor

    4.57
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    Q- Factor Calculation in RL,RC and RLC Circuits

    9.51
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    Relation between Q factor and Bandwidth

    6.22
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    GATE Numericals on A.C. Cricuits _ Part 1

    31.44
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    Transfer Function from State Space Model

    48.37
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    Introduction to Canonical Forms

    12.52
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    Controllable Canonical Form

    45.24
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    GATE Numericals on A.C. Cricuits _ Part 2

    17.35
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    GATE Numericals on A.C. Cricuits _ Part 3

    19
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    GATE Numericals on A.C. Cricuits _ Part 4

    30.44
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    Observable Canonical Form

    9.26
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    Examples on Controllable Canonical Form and Observable Canonical Form

    16.49
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    Diagonal Canonical Form

    25.24
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    Jordan’s Canonical Form

    12.39
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    Examples on Diagonal Canonical Form and Jordan Canonical Form

    37.29
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    Introduction to Graph Theory

    19.22
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    Incidence, Cutset and Tieset Marix

    29.17
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    GATE numericals on Graph Theory _ Part 1

    12.48
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    GATE numericals on Graph Theory _ Part 2

    12.45
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    Stability Using State Space

    25.03
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    Solution to State Space Equations (Inverse Laplace Transform Approach)

    58.19
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    Solution to State Space Equations (Cayley Hamilton Theorem)

    39.06
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    Introduction to Coupling factor and Mutual Inductance

    18.24
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    Numericals on Magnetically Coupled Circuit

    15.15
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    Solution to State Space Equations When Input is Non-Zero

    50.05
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    Concept of Controllability and Observability

    23.36
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    Numericals on State Space Analysis

    36.29
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    Numericals Part 01

    60.01
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    Numericals Part 02

    41.26
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    Numericals Part 03

    26.36
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    Numericals Part 04

    46.42
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    Numericals Part 05

    22.06
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    Digital Circuit - Topic wise test

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