Register For Space App Hackathon
  • ₹ 399
  • ₹ 3000
  • 296 Lectures
  • 56 Hrs videos

Analog and Digital Electronics-North Maharashtra University-Electrical Engineering-SEM IV

This course is explained here:

  • Prasad Soman
  • 2 viewers

Requirements

    No Records To Display

What am I going to get from this course?

No Records To Display
Total Chapters : 6 296 Videos
Concept of Load and Line Regulation in Power Supply
Preview
4.19
BJT: Introduction
Preview
12.46
BJT : Construction
Preview
13.49
BJT : Working
21.16
Characteristics of BJT - CB,CC CE Mode of BJT
21.51
Current Voltage Relationship
17.01
Input Output Characteristics of BJT
11.32
Thermal Runaway
8.07
Early Effect
20.06
Load Line Concept
17
Concept of Stability and Stability Factor
16.34
DC Analysis With BJT Circuit
10.01
Biasing Technique Types
8.5
BJT with Fixed Bias
18.57
BJT with Collector to Base Bias
11.56
BJT with Voltage Divider Bias
22.54
Numerical Example 1on DC analysis of BJT
11.07
Numerical Example 2on DC analysis of BJT
11.33
Numerical Example 3on DC analysis of BJT
9.3
Numerical Example 4 on DC analysis of BJT
12.53
Numerical Example 5on DC analysis of BJT
12.07
Numerical Example 6on DC analysis of BJT
18.56
Modelling styles of BJT and FET(re model , hybrid model h-Parameter model)
22.11
AC Analysis of CE amplifier (with bypass capacitor )
30.46
AC Analysis of CE amplifier (without bypass capacitor )
24.28
AC Analysis of CC amplifier
18.39
AC Analysis of CB amplifier
18.49
Numerical 01- AC Analysis CE - With Bypass Capacitor
28.59
Numerical 2 : AC Analysis CE-without Bypass Capacitor
29.52
FET Concept, Types, Symbol
22.4
JFET : Construction Working and Characteristics
31.21
DC Analysis of FET
14.06
Numerical Example 1 : FET DC Analysis
12.11
Numerical Example 2 : FET DC Analysis
8.06
Numerical Example 3 : FET DC Analysis
13.28
Numerical Example 4 : FET DC Analysis
12.14
CG,CD,CSmode of FET
18.2
Numerical Example 5 : On DC Analysis of JFET
15.3
Parameters of AC analysis
12.48
AC analysis of CS amplifier (with bypass capacitor )
19.43
AC analysis of CS amplifier (with unbypass capacitor )
27.45
AC analysis of CG amplifier
27.12
AC analysis of CD amplifier
21.47
numerical example 1 : CS amplifier(with bypass).
21.53
numerical example 2 : CS amplifier (without bypass)
19.57
Numerical example 3 : CG amplifier
16.58
Numerical example 4 : CD amplifier
19.33
Comparitive Study of CS,CD,CG Amplifier
9.23
Millers Theorem
10.2
High Frequency Analysis
12.06
High Frequency Analysis of BJT
15.18
Numericals on HF analysis of BJT
17.28
FET High Frequency Analysis
20.29
Alpha , Beta Cut off Frequency
40.24
Numericals 1 on High Frequency analysis of BJT
17.26
Numerical 2 High Frequency Analysis on FET
18.14
Numericals on alpha , beta cut off frequency
10.26
Introduction of Logic Gates
Preview
3
Types of Logic Gates - A) AND Gate
Preview
5.05
Types of Logic Gates-B) OR Gate
Preview
4.21
Types of Logic Gate - C) NOT Gate
3.34
Types of Logic Gate - D) NAND Gate
5.55
Types of Logic Gate - E) NOR Gate
5.24
Types of Logic Gate - F) EX - OR Gate
7.45
Types of Logic Gate - G) EX - NOR Gate
6.55
Realization of Basic Gates Using Nand Gate
Preview
8.33
Realization of Basic Gates Using nor Gate
Preview
7.14
DeMorgans Theorem
Preview
10.2
Boolean Laws
Preview
5.46
Boolean Laws Example -1
Preview
4.27
Boolean Laws Example -2
3.31
Boolean Laws Example -3
3.1
Boolean Laws Example -4
4.4
Boolean Laws Example -5
3.09
Introduction to Sum of Product(SOP) and Product of Sum(POS)
Preview
5.21
Standard SOP Form and Standard POS Form
Preview
9.3
Conversion of Logical Expression to SOP Form
7.21
Conversion of logical Expression to POS Form
8.39
Concept of Min Term in Logical Expression
4.53
Concept of Max Term in Logical Expression
5
Represention of Logical Expression Using Min Term
5.53
Represention of Logical Expression Using Max Term
6.33
Realize Logical Expression Using Basic Logic Gates
13.52
Basic Logical Operator
Preview
5.03
Intoduction to K-map
Preview
8.25
Mapping of Truth Table to K-Map
Preview
7.11
Represent SOP Expression on K-Map
10.37
Represent POS Expression on K-Map
8.41
Grouping of Two Adjacent 1's on K-Map
10.33
Grouping of Three Adjacent 1's on K-Map
9.35
Grouping of Four Adjacent 1's on K-Map
11.58
Grouping of Eight Adjacent 1's on K-Map
8.04
Sop Numerical Based on K-Map Type-1
Preview
11.47
Sop Numerical Based on K-Map Type-2
13.07
Sop Numerical Based on K-Map Type-3
19.15
Sop Numerical Based on K-Map Type-4
15.51
Pos Numerical Based on K-Map Type-1
Preview
15.14
Pos Numerical Based on K-Map Type-2
17.24
Pos Numerical Based on K-Map Type-3
28.18
Pos Numerical Based on K-Map Type-4
17.43
Introduction to Logic Family
4.07
Classification of Logic Family
Preview
6.56
Bipolar logic family
5.38
Unipolar Logic Family
3.47
Classification Based on Circuit Complexity
4.26
Comparison of CMOS & TTL
4.39
Comparison of TTL,CMOS,ECL
5.08
Introduction to Analog and Digital Signals
2.44
BCD Adder
3.43
Carry Look Ahead Adder
2.45
Introduction and types of number system
Preview
6.16
Concept of binary multiplication
Preview
6.03
Binary number system to decimal number system
Preview
6.23
Binary number system to Octal number system
6.17
Binary number system to Hexadecimal number system
6.33
Decimal number system to Binary number system
Preview
7.03
Decimal number system to Octal number system
6.11
Decimal number system to Hexadecimal number system
6.57
Octal number system to Binary number system
Preview
4.53
Hexadecimal number system to Binary number system
6.25
Octal number system to Hexadecimal number system
7.41
Hexadecimal number system to Octal number system
7.03
Octal number system to decimal number system
Preview
4.09
Hexadecimal number system to decimal number system
5.54
1's compliment and 2's compliment
Preview
7.08
Binary addition and binary subtraction
Preview
5.37
Examples an 1's and 2's compliments
12.58
Binary subtraction using 2's compliment-Example-1
Preview
6.04
Binary subtraction using 2's compliment-Example-2
4.47
Binary subtraction using 2's compliment-Example-3
5.31
Introduction to codes
Preview
16.15
Conversion of binary code to BCD code Example-1
Preview
4.57
Conversion of binary code to BCD code Example-2
4.23
Conversion of binary code to BCD code Example-3
4.03
Conversion of BCD code to Binary code Example-1
Preview
4.48
Conversion of BCD code to Binary code Example-2
4.14
Conversion of BCD code to Binary code Example-3
4.37
Conversion of BCD code to Excess-3 code Example-1
Preview
3.23
Conversion of BCD code to Excess-3 code Example-2
4.06
Conversion of BCD code to Excess-3 code Example-3
3.13
Conversion of Excess-3 code to BCD code Example-1
Preview
5.29
Conversion of Excess-3 code to BCD code Example-2
4.5
Conversion of Excess-3 code to BCD code Example-3
4.47
Concept of binary logic and logic levels
Preview
6.23
Numerical Based on QM Method Example -1
Preview
18.12
Numerical Based on QM Method Example -2
11.03
Numerical Basedon QM Method Example -3
21.33
Numerical based on QM Method Example -4
21.26
Numerical based on QM Method Example -5
20.11
Numerical Based on QM Method Example -6
18.04
Half Adder Circuit
Preview
12.37
Full Adder Circuit
Preview
18.51
Half Subtractor Circuit
10.56
Full subtractor
19.48
1 bit magnitude comparator
14
4 bit parallel adder circuit
7.48
n-bit parallel adder circuit
5.35
Introduction to multiplexer
Preview
4.52
Explain 4:1 MUX
Preview
10.56
Numerical based on multiplexer type-1- Example-1
Preview
5.37
Numerical based on multiplexer type-1- Example-2
5.19
Numerical based on multiplexer type-1- Example-3
4.06
Numerical based on multiplexer type-2- Example-1
Preview
4.37
Numerical based on multiplexer type-2- Example-2
4.33
Numerical based on multiplexer type-3- Example-1
6.48
Numerical based on multiplexer type-3- Example-2
6.25
Numerical based on multiplexer type-3- Example-3
6.24
Numerical based on multiplexer type-4- Example-1
Preview
5.39
Numerical based on multiplexer type-4- Example-2
6.15
Numerical based on multiplexer type-4- Example-3
4.54
Numerical based on multiplexer type-5- Example 1
7.13
Numerical based on multiplexer type-5- Example2
7.24
Implement full adder using 8:1 MUX
Preview
9.51
Introduction to DEMUX
Preview
7.12
Explanation to 1:8 Demultiplexer
6.21
Numerical based on demultiplexer type-1- Example-1
Preview
6.51
Numerical based on demultiplexer type-1- Example-2
5.31
Numerical based on demultiplexer type-2- Example-1
6.05
Numerical based on demultiplexer type-2- Example-2
5.09
Numerical based on demultiplexer type-3- Example-1
7.13
Numerical based on demultiplexer type-3- Example-2
7.25
Implement full subtractor using 1:8 DEMUX
Preview
8.21
Implement full adder using 1:8 DEMUX
8.28
Introduction to Encoder
Preview
3.47
Decimal to BCD encoder
Preview
9.46
Octal to binary encoder
7.3
Hexadecimal to binary encoder
10.54
Introduction to decoder
6.48
Numerical based on decoder type-1- EX-1
3.5
Numerical based on decoder type-1- EX-2
5.08
Numerical based on decoder type-2- EX-1
6.37
Numerical based on decoder type-2- EX-2
6.4
Design of Series Adder FSM
Preview
3.14
Design of Vending Machine
4.26
Universal Shift Register
2.36
Frequency Division
3.31
Implication Cable Method
7.16
Comparison of Mealy and Moore circuit
3.39
Introduction to Flipflop
Preview
3.39
SR-FF
Preview
18.47
JK-FF
Preview
16.26
MSJK-FF
2.4
D-FF
4.41
T-FF
4.38
Conversion of SRFF to DFF
Preview
7.56
Conversion of JKFF to TFF
7.09
Conversion of SRFF to TFF
8.03
Conversion of SRFF to JKFF
9.49
Conversion of DFF to TFF
6.06
Conversion of T-FF to D-FF
7.53
Conversion of JKFF to SRFF
8.27
Conversion of DFF to JKFF
7.45
Conversion of TFF to JKFF
5.37
Concept of Preset & Clear in Flipflops
5.25
Difference Between Combinational Circuit and Sequential Circuit
Preview
5.03
Introduction to Counters
Preview
4.2
3 Bit Asynchronous Up Counter
12.44
4 Bit Asynchronous Up Counter
14.4
3 Bit Asynchronous Down Counter
11.03
4 Bit Asynchronous Down Counter
13.33
3 Bit Asynchronous Up-Down Counter
10.26
Introduction to Modulus of Counter
Preview
4.05
Design Mod-6 Asynchronous Counter Using JK-FF
Preview
9
Design MOD-13 Ripple Counter Using JK-FF
8.06
Design Decade Ripple Counter
7.19
Design 2 Bit Synchronous up Counter
14.26
Design 3 Bit Synchronous up Counter using TFF
16.6
Design 3 Bit Synchronous Up Counter Using JKFF
21.27
Design Synchronous Decade Counter Using TFF
33.24
Design Mod-12 Synchronous Counter Using JKFF
40.39
Design Mod-10 Synchronous Counter Using JKFF
36.1
Design Synchronous Counter Using T-FF Example 1
Preview
24.33
Design Synchronous Counter Using T-FF Example 2
15.51
Design Synchronous Counter Using T-FF Example 3
16.37
Design of 3 Bit Updown Synchronous Counter
Preview
20.45
Introduction to Registers
Preview
3.41
Data formats for Registers
Preview
4.35
Classification of Registers
8.15
Serial Input Serial Output
9.4
Serial Input Parallel Output
4.43
Parallel Input Parallel Output
4.58
Parallel Input Serial Output
4.42
Applications of Shift Registers
4.28
Design Synchronous Counter Ex-4
18.45
Ring Counter
6.44
Johnson Counter
Preview
6.44
Characteristics of Logic Family
Preview
4.28
Introduction to Mealy Circuit
4.05
Introduction to Moore circuit
3.38
Numerical Based on ROW Elimination Methods Example 1
17.42
Numerical Based on Row Elimination Methods Example 2
10.53

Frequently bought together

About the Instructor

Prasad Soman

Instructor and teacher

Ekeeda is India's leading online technical educational platform. We work with Technical students and Professional to impart technical knowledge anytime, anywhere.

  • ₹ 399