More about Threshold Voltage:
The nMOS transistor is used for discussion here.
Let the nMOS transistor is connected as shown in Figure 17
Figure 17: nMOS Transistor with voltages
Let the Gate Voltage VG be made positive (greater than Zero voltage).
The Gate, the thin Oxide (Dielectric) and the substrate form a Capacitor.
As VG becomes positive, the holes in the P Substrate are repelled away from the Gate. leaving behind immobile negative ions.
The charge of the negative ions mirrors the charge on the Gate.
Under these conditions a depletion region is formed under the Gate area as the holes are repelled away from the Gate. There is no current flow because there are no charge carriers.
The Width of the Depletion region and the Potential at the Oxide - Silicon interface is directly proportional to the Gate Voltage VG i.e. they increase with increase in Gate Voltage
This phenomenon can be visualized as a voltage divider of two series capacitors - Gate Oxide Capacitor and Depletion region Capacitor.
This is the onset of inversion and shown in Figure 18.
Figure 18: Onset of Inversion
As the Gate potential still further increases and becomes sufficiently positive, electrons start flowing from the Source to the Interface and eventually to the Drain. The results in a channel of charge carriers (electrons here) under the Gate Oxide between the Source and Drain and the Transistor turns ON and the interface is Inverted.
The Gate Voltage at which this happens is called the Threshold Voltage VTH.
Further increase in VG, the charge in the depletion region remains relatively constant and the channel charge density increases. This results in an increased current from Source to Drain.
The Threshold Voltage VTH of nMOS is given as:
𝚽MS = Difference of work functions of Polysilicon Gate and Silicon Substrate
For a pMOS transistor, the operation is exactly reversed and all the polarities are reversed. The Threshold Voltage is negative. .
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