Processor Organization

Processor Organization

All computers are designed based on the Von Neumann model.In this model:

  1. Data and Instructions are stored in single read / write memory.

  2. The memory can be addressed by a unique address.

  3. Execution of instructions takes place in a sequential fashion.

The basic function of the computer is instruction execution. The instructions are there in the main memory and the processor fetches the instruction one by one and executes the instruction. The instruction execution may involve several stages and different fetch operations to get the data. The processing required to complete the execution of one instruction is called instruction cycle.

System Bus Architecture

The Computer system contains bus interconnects to connect various components of the system at various hierarchical levels. The bus connections are called as system bus as shown in Figure 9, comprises of:

  1. Data Bus
    To carry the data bits from or to memory or I/O.The width of the data bus governs the system performance. For example - If the data bus is 16-bits in width and a 32-bit word is to  be fetched from the memory, then the processor has to perform two memory read operations.

  2. Address Bus
    To carry the address bits from where the data or instruction is to be fetched. The size of the address bus determines the maximum memory capacity of the system. If the size of the address bus is 8-bits, the number of unique locations are 28=256. If the memory is word addressable then its capacity is 256 words.

  3. Control Bus
    To carry the control signals to synchronize the operations. Some of the control signals can be memory read, memory write etc.

Figure 9 : System Bus Architecture

Instruction Cycle

The instruction cycle is divided into two stages. Fetch stage and Execute stage as shown in Figure 10.

Figure 10: Basic Instruction Cycle

  • Fetch Cycle
    The processor fetches the instruction from the memory. The address of the next instruction is present in a register called program counter (PC). The PC is always incremented to get the next instruction unless it is specified. The fetched instruction is stored in a register called instruction register (IR).

  • Execute Cycle
    The instruction consists of two parts namely - 

  1. Opcode
    Code that specifies the processor about the action to be taken. For example ADD, SUB etc.

  2. Operands
    The data on which the specified action has to take place. For Example ADD a, b where a,b are operands.

The fetched instruction is decoded by the processor to understand the action to be taken. The processor interprets the instruction and takes different actions. The actions broadly fall into four categories- 

  1. Processor-Memory
    Data is transferred from processor to memory or vice versa.

  2. Processor-I/O
    Data is transferred from processor to I/O device or vice versa.

  3. Data Processing
    The processor may perform ALU operations on the data.

  4. Control
    The sequence of execution may be altered after the interpretation of the instruction.