- Introduction and Types of Number System
- Concept of Binary Multiplication
- Binary Number System to Decimal Number System
- Binary Number System to Octal Number System
- Binary Number System to Hexadecimal Number System
- Decimal Number System to Binary Number System
- Decimal Number System to Octal Number System
- Decimal Number System to Hexadecimal Number System
- Octal Number System to Binary Number System
- Hexadecimal Number System to Binary Number System
- Octal Number System to Hexadecimal Number System
- Hexadecimal Number System to Octal Number System
- Octal Number System to Decimal Number System
- Hexadecimal Number System to Decimal Number System
- 1's Compliment and 2's Compliment
- Binary Addition and Binary Subtraction
- Examples an 1's and 2's Compliments
- Binary Subtraction Using 2's Compliment-Example-1
- Binary Subtraction Using 2's Compliment-Example-2
- Binary Subtraction Using 2's Compliment-Example-3
- Introduction to Codes
- Conversion of Binary Code to BCD Code Example-1
- Conversion of Binary Code to BCD Code Example-2
- Conversion of Binary Code to BCD Code Example-3
- Conversion of BCD Code to Binary Code Example-1
- Conversion of BCD Code to Binary Code Example-2
- Conversion of BCD Code to Binary Code Example-3
- Conversion of BCD Code to Excess-3 Code Example-1
- Conversion of BCD Code to Excess-3 Code Example-2
- Conversion of BCD Code to Excess-3 Code Example-3
- Example on Conversion of Excess -3 Code to BCD Code
- Concept of Binary Logic and Logic Levels
- Numerical Based on QM Method Example -1
- Numerical Based on QM Method Example -2
- Numerical Basedon QM Method Example -3
- Numerical based on QM Method Example -4
- Numerical based on QM Method Example -5
- Numerical Based on QM Method Example -6
- Half Adder Circuit
- Full Adder Circuit
- Half Subtractor Circuit
- Full Subtractor
- 1 Bit Magnitude Comparator
- 4 Bit Parallel Adder Circuit
- N-Bit Parallel Adder Circuit
- Introduction to Multiplexer
- Explain 4:1 MUX
- Numerical Based on Multiplexer Type-1- Example-1
- Numerical Based on Multiplexer Type-1- Example-2
- Numerical Based on Multiplexer Type-1- Example-3
- Numerical Based on Multiplexer Type-2- Example-1
- Numerical Based on Multiplexer Type-2- Example-2
- Numerical Based on Multiplexer Type-3- Example-1
- Numerical Based on Multiplexer Type-3- Example-2
- Numerical Based on Multiplexer Type-3- Example-3
- Numerical Based on Multiplexer Type-4- Example-1
- Numerical Based on Multiplexer Type-4- Example-2
- Numerical Based on Multiplexer Type-4- Example-3
- Numerical Based on Multiplexer Type-5- Example 1
- Numerical Based on Multiplexer Type-5- Example2
- Implement Full Adder using 8:1 MUX
- Introduction to DEMUX
- Explanation to 1:8 Demultiplexer
- Numerical Based on Demultiplexer Type-2- Example-1
- Numerical Based on Demultiplexer Type-2- Example-2
- Numerical based on demultiplexer type-2- Example-1
- Numerical based on demultiplexer type-2- Example-2
- Numerical Based on Demultiplexer Type-3- Example-1
- Numerical Based on Demultiplexer Type-3- Example-2
- Implement Full Subtractor using 1:8 DEMUX
- Implement Full Adder using 1:8 DEMUX
- Introduction to Encoder
- Decimal to BCD encoder
- Octal to Binary Encoder
- Hexadecimal to Binary Encoder
- Introduction to Decoder
- Numerical Based on Decoder Type-1- Ex-1
- Numerical Based on Decoder Type-1- Ex-2
- Numerical Based on Decoder Type-2- Ex-1
- Numerical Based on Decoder Type-2- Ex-2

- Introduction of Logic Gates
- Types of Logic Gates - A) AND Gate
- Types of Logic Gates-B) OR Gate
- Types of Logic Gate - C) NOT Gate
- Types of Logic Gate - D) NAND Gate
- Types of Logic Gate - E) NOR Gate
- Types of Logic Gate - F) EX - OR Gate
- Types of Logic Gate - G) EX - NOR Gate
- Realization of Basic Gates using NAND gate
- Realization of Basic Gates using NOR gate
- DeMorgans Theorem
- Boolean Laws
- Boolean Laws Example -1
- Boolean Laws Example -2
- Boolean Laws Example -3
- Boolean Laws Example -4
- Boolean Laws Example -5
- Introduction to Sum of Product(SOP) and Product of sum(POS)
- Standard SOP Form and Standard POS Form
- Conversion of Logical Expression to SOP Form
- Conversion of Logical Expression to POS Form
- Concept of Min Term in Logical Expression
- Concept of Max Term in Logical Expression
- Representation of Logical Expression Using Min Term
- Representation of Logical Expression Using Max Term
- Realize Logical Expression Using Basic Logic Gates
- Basic Logical Operator
- Introduction to K-Map
- Mapping of Truth Table to K-Map
- Represent SOP Expression on K-Map
- Representors Expression on K-Map
- Grouping of Two Adjacent 1's on K-Map
- Grouping of Three Adjacent 1's on K-Map
- Grouping of Four Adjacent 1's on K-Map
- Grouping of Eight Adjacent 1's on K-Map
- SOP Numerical based on K-map Type-1
- SOP Numerical based on K-map Type-2
- SOP Numerical based on K-map Type-3
- SOP Numerical based on K-map Type-4
- POS Numerical based on K-map Type-1
- POS Numerical based on K-map Type-2
- POS Numerical based on K-map Type-3
- POS Numerical based on K-map Type-4
- Introduction to Logic Family
- Characteristics of Logic Family
- Classification of Logic Family
- Bipolar Logic Family
- Unipolar Logic Family
- Classification Based on Circuit Complexity
- Comparison of CMOS and TTL
- Comparison of TTL, CMOS, ECL
- Introduction to Analog and Digital Signals
- BCD Adder
- Carry Look Ahead Adder

- Introduction to Sequential Logic Circuit
- Difference Between Combinational Circuit and Sequential Circuit
- SR Latch Introduction
- What is Clock Signal?
- Introduction to Flip Flop
- SR-FF
- JK-FF
- MSJK-FF
- D-FF
- T-FF
- Conversion of JKFF to DFF
- Conversion of SRFF to DFF
- Conversion of JKFF to TFF
- Conversion of SRFF to TFF
- Conversion of SRFF to JKFF
- Conversion of DFF to TFF
- Conversion of T-FF to D-FF
- Conversion of JKFF to SRFF
- Conversion of DFF to JKFF
- Conversion of TFF to JKFF
- Concept of Preset & Clear in Flipflops
- Introduction to Counters
- 3 Bit Asynchronous Up Counter
- 4 Bit Asynchronous Up Counter
- 3 Bit Asynchronous Down Counter
- 4 Bit Asynchronous Down Counter
- 3 Bit Asynchronous Up-Down Counter
- Introduction to Modulus of Counter
- Design MOD-6 Asynchronous Counter using JK-FF
- Design MOD-13 Ripple Counter using JK-FF
- Design Decade Ripple Counter
- Frequency Division
- Design 2 Bit Synchronous Up Counter
- Design 3 Bit Synchronous Up Counter using TFF
- Design 3 Bit Synchronous Up Counter using JKFF
- Design Synchronous Decade Counter using TFF
- Design Mod-12 Synchronous Counter using JKFF
- Design Mod-10 Synchronous Counter using JKFF
- Design Synchronous Counter Using T-FF Example 1
- Design Synchronous Counter Using T-FF Example 2
- Design Synchronous Counter Using T-FF Example 3
- Design of 3 Bit Updown Synchronous Counter
- Design Synchronous Counter Ex-4
- Introduction to Registers
- Data Formats for Registers
- Classification of Registers
- Serial Input Serial Output
- Serial Input Parallel Output
- Parallel Input Parallel Output
- Parallel Input Serial Output
- Universal Shift Register
- Applications of Shift Registers
- Ring Counter
- Johnson Counter
- Introduction to Mealy Circuit
- Introduction to Moore Circuit
- Comparison of Mealy and Moore circuit
- Implication Cable Method
- Numerical Based on ROW Elimination Methods Example 1
- Numerical Based on Row Elimination Methods Example 2
- Design of Series Adder FSM
- Design of Vending Machine

- Introduction to VHDL
- Introduction Of Identifies
- Important Points While Designing Any Module Using VHDL
- Implimentation Priority Encoder Using VHDL
- VHDL Code for Fibonacci Series Generator
- Features of VHDL
- VHDL Operators
- Structure of VHDL
- Introduction to Package
- Introduction to Entity
- Introduction to Architecture
- Introduction to Library
- Structural Modeling in VHDL
- Dataflow Modeling in VHDL
- Behavioval Style of Modeling in VHDL
- VHDL Data Objects
- VHDL Data Types
- VHDL Code to Implement NOT GATE
- VHDL Code to Implement NOR GATE
- VHDL Code to Implement XOR GATE
- VHDL Code to Implement XNOR GATE
- VHDL Code to Implement AND GATE
- VHDL Code to Implement OR GATE
- VHDL Code to Implement NAND GATE
- Implementation of Full Adder Using VHDL Code and Considering data Flow Modeling
- Implementation of Half Subtractor Using NHDL Code Considering Dataflow Modeling
- Implementation of Full Subtractor using VHDL Code Considering Dataflow

- Introduction to Programmable Logic Devices
- Keyboard Devices
- Uses of PLDs
- Advantages of PLDs
- Programmable Logic Array
- Programmable Array Logic
- Complex Programmable Logic Devices
- Field Programmable Gate Array
- Example based on PLA Ex-1
- Example based on PLA Ex-2
- Example based on PAL Ex-1
- Comparison between PLA & PAL
- Example Based on PAL Example - 2
- Difference Between CPLD and FPGA

Professor Payal Varangaonkar has attained Master's degree in Engineering with her specialization subject as Electronics and Telecommunications. In addition to it, she is currently pursuing Ph.D. in Electronics and Telecommunications from Amaravati University. She has over 8 years of teaching experience and 2 years of work experience in the Industrial area. Her core areas of Engineering are Digital System Design, Principles of Communication Engineering, Basic Electronics and Electrical. Her Practical Knowledge with an Innovative Approach makes her an absolute extraordinary mentor.

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