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  • lecture147 Lectures
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Digital Electronics-Pune University-Electronics Engineering-SEM III

This course is explained here:

  • Payal Varangaonkar
  • 5 viewers

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Total Chapters : 6 147 Videos
Introduction of Logic Gates
Preview
3
Types of Logic Gates - A) AND Gate
Preview
5.05
Types of Logic Gates-B) OR Gate
Preview
4.21
Types of Logic Gate - C) NOT Gate
3.34
Types of Logic Gate - D) NAND Gate
5.55
Types of Logic Gate - E) NOR Gate
5.24
Types of Logic Gate - F) EX - OR Gate
7.45
Types of Logic Gate - G) EX - NOR Gate
6.55
Realization of Basic Gates Using Nand Gate
Preview
8.33
Realization of Basic Gates Using nor Gate
Preview
7.14
DeMorgans Theorem
Preview
10.2
Boolean Laws
Preview
5.46
Boolean Laws Example -1
Preview
4.27
Boolean Laws Example -2
3.31
Boolean Laws Example -3
3.1
Boolean Laws Example -4
4.4
Boolean Laws Example -5
3.09
Introduction to Sum of Product(SOP) and Product of Sum(POS)
Preview
5.21
Standard SOP Form and Standard POS Form
Preview
9.3
Conversion of Logical Expression to SOP Form
7.21
Conversion of logical Expression to POS Form
8.39
Concept of Min Term in Logical Expression
4.53
Concept of Max Term in Logical Expression
5
Represention of Logical Expression Using Min Term
5.53
Represention of Logical Expression Using Max Term
6.33
Realize Logical Expression Using Basic Logic Gates
13.52
Basic Logical Operator
Preview
5.03
Intoduction to K-map
Preview
8.25
Mapping of Truth Table to K-Map
Preview
7.11
Represent SOP Expression on K-Map
10.37
Represent POS Expression on K-Map
8.41
Grouping of Two Adjacent 1's on K-Map
10.33
Grouping of Three Adjacent 1's on K-Map
9.35
Grouping of Four Adjacent 1's on K-Map
11.58
Grouping of Eight Adjacent 1's on K-Map
8.04
Sop Numerical Based on K-Map Type-1
Preview
11.47
Sop Numerical Based on K-Map Type-2
13.07
Sop Numerical Based on K-Map Type-3
19.15
Sop Numerical Based on K-Map Type-4
15.51
Pos Numerical Based on K-Map Type-1
Preview
15.14
Pos Numerical Based on K-Map Type-2
17.24
Pos Numerical Based on K-Map Type-3
28.18
Pos Numerical Based on K-Map Type-4
17.43
Introduction to Logic Family
4.07
Classification of Logic Family
Preview
6.56
Bipolar logic family
5.38
Unipolar Logic Family
3.47
Classification Based on Circuit Complexity
4.26
Comparison of CMOS & TTL
4.39
Comparison of TTL,CMOS,ECL
5.08
Introduction to Analog and Digital Signals
2.44
BCD Adder
3.43
Carry Look Ahead Adder
2.45
Design of Series Adder FSM
Preview
3.14
Design of Vending Machine
4.26
Universal Shift Register
2.36
Frequency Division
3.31
Implication Cable Method
7.16
Comparison of Mealy and Moore circuit
3.39
Introduction to Flipflop
Preview
3.39
SR-FF
Preview
18.47
JK-FF
Preview
16.26
MSJK-FF
2.4
D-FF
4.41
T-FF
4.38
Conversion of SRFF to DFF
Preview
7.56
Conversion of JKFF to TFF
7.09
Conversion of SRFF to TFF
8.03
Conversion of SRFF to JKFF
9.49
Conversion of DFF to TFF
6.06
Conversion of T-FF to D-FF
7.53
Conversion of JKFF to SRFF
8.27
Conversion of DFF to JKFF
7.45
Conversion of TFF to JKFF
5.37
Concept of Preset & Clear in Flipflops
5.25
Difference Between Combinational Circuit and Sequential Circuit
Preview
5.03
Introduction to Counters
Preview
4.2
3 Bit Asynchronous Up Counter
12.44
4 Bit Asynchronous Up Counter
14.4
3 Bit Asynchronous Down Counter
11.03
4 Bit Asynchronous Down Counter
13.33
3 Bit Asynchronous Up-Down Counter
10.26
Introduction to Modulus of Counter
Preview
4.05
Design Mod-6 Asynchronous Counter Using JK-FF
Preview
9
Design MOD-13 Ripple Counter Using JK-FF
8.06
Design Decade Ripple Counter
7.19
Design 2 Bit Synchronous up Counter
14.26
Design 3 Bit Synchronous up Counter using TFF
16.6
Design 3 Bit Synchronous Up Counter Using JKFF
21.27
Design Synchronous Decade Counter Using TFF
33.24
Design Mod-12 Synchronous Counter Using JKFF
40.39
Design Mod-10 Synchronous Counter Using JKFF
36.1
Design Synchronous Counter Using T-FF Example 1
Preview
24.33
Design Synchronous Counter Using T-FF Example 2
15.51
Design Synchronous Counter Using T-FF Example 3
16.37
Design of 3 Bit Updown Synchronous Counter
Preview
20.45
Introduction to Registers
Preview
3.41
Data formats for Registers
Preview
4.35
Classification of Registers
8.15
Serial Input Serial Output
9.4
Serial Input Parallel Output
4.43
Parallel Input Parallel Output
4.58
Parallel Input Serial Output
4.42
Applications of Shift Registers
4.28
Design Synchronous Counter Ex-4
18.45
Ring Counter
6.44
Johnson Counter
Preview
6.44
Characteristics of Logic Family
Preview
4.28
Introduction to Mealy Circuit
4.05
Introduction to Moore circuit
3.38
Numerical Based on ROW Elimination Methods Example 1
17.42
Numerical Based on Row Elimination Methods Example 2
10.53

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About the Instructor

Payal Varangaonkar

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Instructor and teacher

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